Hi.
I am implementing pixel data transfer via SPI + DMA on Raspberry PI 3B+
I have an ili9341 display and I want to output 320x240x3 bytes of data over SPI with the help of DMA
I have read carefully BCM2835 Arm Peripherals doc.
Page 158 10.6.3 DMA seemingly explains what I need to, but this does not work.
Before sending pixel data, I do some preparations:
1. I first flush SPI fifo and reset dma channels, SPI_CS |= 3<<4 for flushing
2. I then setup a chain of TX channel control blocks.
2.1. First control block is a 4byte header with transfer size and SPI_CS flags, its next field points to data control block
2.2. Second control block is data
3. I then setup a chain of RX channel control blocks, this is one step easier, I just chain several successive data control blocks
4. I also assure that as soon as header+data are completely serviced by DMA channel for SPI TX, I start next pair of header + data, describing next pixel data.
Below is the printout of control block setup.
All control blocks are located in noncached memory usable for DMA needs.This of course did not work.
Can anyone point to why chain-dma did not work?
Also, I have found that RX IRQ never worked as well even on simpler examples exactly as in documentation
I am implementing pixel data transfer via SPI + DMA on Raspberry PI 3B+
I have an ili9341 display and I want to output 320x240x3 bytes of data over SPI with the help of DMA
I have read carefully BCM2835 Arm Peripherals doc.
Page 158 10.6.3 DMA seemingly explains what I need to, but this does not work.
Before sending pixel data, I do some preparations:
1. I first flush SPI fifo and reset dma channels, SPI_CS |= 3<<4 for flushing
2. I then setup a chain of TX channel control blocks.
2.1. First control block is a 4byte header with transfer size and SPI_CS flags, its next field points to data control block
2.2. Second control block is data
3. I then setup a chain of RX channel control blocks, this is one step easier, I just chain several successive data control blocks
4. I also assure that as soon as header+data are completely serviced by DMA channel for SPI TX, I start next pair of header + data, describing next pixel data.
Below is the printout of control block setup.
All control blocks are located in noncached memory usable for DMA needs.
Code:
DMA Channel 0: SPI TX cb:01f4c000,TI:04060148,c1f21000->7e204004(00000004),next:c1f4c020,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c020,TI:04060148,c204c000->7e204004(0000fff8),next:c1f4c060,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c060,TI:04060148,c1f21004->7e204004(00000004),next:c1f4c080,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c080,TI:04060148,c205bff8->7e204004(0000fff8),next:c1f4c0c0,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c0c0,TI:04060148,c1f21008->7e204004(00000004),next:c1f4c0e0,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c0e0,TI:04060148,c206bff0->7e204004(0000fff8),next:c1f4c120,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c120,TI:04060148,c1f2100c->7e204004(00000004),next:c1f4c140,-WAd: 32rq---s:++ 32 B0,P6,W0 cb:01f4c140,TI:04060149,c207bfe8->7e204004(00008418),next:00000000,IWAd: 32rq---s:++ 32 B0,P6,W0 DMA Channel 1: SPI RX cb:01f4c040,TI:04070408,7e204004->c0eb4080(0000fff8),next:c1f4c0a0,-WAd: 32-----s: 32rqB0,P7,W0 cb:01f4c0a0,TI:04070408,7e204004->c0eb4080(0000fff8),next:c1f4c100,-WAd: 32-----s: 32rqB0,P7,W0 cb:01f4c100,TI:04070408,7e204004->c0eb4080(0000fff8),next:c1f4c160,-WAd: 32-----s: 32rqB0,P7,W0 cb:01f4c160,TI:04070409,7e204004->c0eb4080(00008418),next:00000000,IWAd: 32-----s: 32rqB0,P7,W0Can anyone point to why chain-dma did not work?
Also, I have found that RX IRQ never worked as well even on simpler examples exactly as in documentation
Statistics: Posted by valc — Thu Mar 07, 2024 4:11 pm