For writes to memory in the uncached XIP address range, does XIP buffer writes? For example, if a processor does an uncached XIP write, is it guaranteed to stall until the QSPI request completes, or can the processor continue while XIP performs the QSPI request in parallel? I don't think Cortex M33 has the smarts for this but, how about reads?
For context, I am working on a design where QMI CS1 is connected to an FPGA. Requests to QMI CS1 would address registers of peripherals in the FPGA, so it doesn't make sense to use the XIP cache, since reading and writing them has other side-effects.
For context, I am working on a design where QMI CS1 is connected to an FPGA. Requests to QMI CS1 would address registers of peripherals in the FPGA, so it doesn't make sense to use the XIP cache, since reading and writing them has other side-effects.
Statistics: Posted by alastairpatrick — Sat Sep 07, 2024 10:23 pm