No, I have no problem, just trying to understand the new retrigger because I don't see its point. For the buffer I use four channels each one covering a 32k sector because I'm transferring data at 3.2Gb/s and if I must wait for the reconfigure and trigger then it would overflow the PIO FIFO, and I could use only two DMA channels and reconfigure the finalized one through an interrupt but that would imply to use the CPU and I would like to avoid it.Ah OK, so your issue is not with the new self-trigger facility but with the 32K limit on the original ring feature (that hasn’t changed).
But you still only need 2 channels- one for the actual transfer (as big as you like) which chains to another one that just transfers one word to the WRITE_ADDR_TRIG (or READ as applicable) to reload the buffer address and restart the transfer. Gives you infinite transfers with no interrupts (or int on wrap if you want but not timing critical). Or if you want multiple interrupts per cycle, again a pair of channels with the interrupt handler adjusting the address in the not-currently-active channel. Or one transfer channel and one reload channel as above, but now the reload channel has a list of buffer addresses (and you can then use ring mode on the list of buffer addresses).
And still, I don't get the purpose of the auto-trigger, if I have a 64k buffer, then I configure the DMA to do 32k transfers and auto-trigger itself, after the second 32k transfer the DMA will overrun the buffer, it will never roll back to the beginning, so, what's the point? That's what I don't get at all, if the channel retriggers itself and the read/write addresses continue were they ended then there is no way to use it for a ring buffer...
Statistics: Posted by Dr.Gusman — Wed Aug 28, 2024 7:48 pm